SI2324DS description the attached spice model desc ribes the typical electrical characteristics of the n-channel vertical dmos. the subcircuit model is extracted and optimized over the - 55 c to + 125 c temperature ranges under the pulsed 0 v to 10 v gate drive. the saturated output impedance is best fit at the gate bias near the threshold voltage. a novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched c gd model. all model parameter values are opti mized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. characteristics ? n-channel vertical dmos ? macro model (subcircuit model) ?level 3 mos ? apply for both linear and switching application ? accurate over the - 55 c to + 125 c temperature range ? model the gate charge, transient, and diode reverse recovery characteristics subcircuit model schematic note ? this document is intended as a spice modeling guideline and do es not constitute a commercial product datasheet. designers shou ld refer to the appropriate datasheet of the same number for guaranteed specification limits. d s dbd c gs m 1 g 3 r 1 m 2 gx r g c gd gy etcv + C product specification 1 of 2 4008-318-123 sales@twtysemi.com http://www.twtysemi.com document number: 63245 www.vishay.com s11-1189-rev. a, 27-jun-11 1 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 n-channel 100 v (d-s) mosfet spice device model SI2324DS vishay siliconix description the attached spice model desc ribes the typical electrical characteristics of the n-channel vertical dmos. the subcircuit model is extracted and optimized over the - 55 c to + 125 c temperature ranges under the pulsed 0 v to 10 v gate drive. the saturated output impedance is best fit at the gate bias near the threshold voltage. a novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched c gd model. all model parameter values are opti mized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. characteristics ? n-channel vertical dmos ? macro model (subcircuit model) ?level 3 mos ? apply for both linear and switching application ? accurate over the - 55 c to + 125 c temperature range ? model the gate charge, transient, and diode reverse recovery characteristics subcircuit model schematic note ? this document is intended as a spice modeling guideline and do es not constitute a commercial product datasheet. designers shou ld refer to the appropriate datasheet of the same number for guaranteed specification limits. d s dbd c gs m 1 g 3 r 1 m 2 gx r g c gd gy etcv + ?
notes a. pulse test; pulse width ? 300 s, duty cycle ? 2 %. b. guaranteed by design, not su bject to production testing. specifications (t j = 25 c, unless otherwise noted) parameter symbol test conditions simulated data measured data unit static gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 1.8 - v drain-source on-state resistance a r ds(on) v gs = 10 v, i d = 1.5 a 0.199 0.195 ? v gs = 6 v, i d = 1 a 0.222 0.222 forward transconductance a g fs v ds = 20 v, i d = 4.6 a 3 2 s body diode voltage v sd i s = 1.3 a 0.79 0.80 v dynamic b input capacitance c iss v ds = 20 v, v gs = 0 v, f = 1 mhz 190 190 pf output capacitance c oss 22 22 reverse transfer capacitance c rss 15 13 total gate charge q g v ds = 50 v, v gs = 10 v, i d = 1.6 a 4.1 5.2 nc v ds = 50 v, v gs = 4.5 v, i d = 1.6 a 2.5 2.9 gate-source charge q gs 0.75 0.75 gate-drain charge q gd 1.4 1.4 SI2324DS product specification 2 of 2 4008-318-123 sales@twtysemi.com http://www.twtysemi.com www.vishay.com document number: 63245 2 s11-1189-rev. a, 27-jun-11 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 spice device model SI2324DS vishay siliconix notes a. pulse test; pulse width d 300 s, duty cycle d 2 %. b. guaranteed by design, not su bject to production testing. specifications (t j = 25 c, unless otherwise noted) parameter symbol test conditions simulated data measured data unit static gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 1.8 - v drain-source on-state resistance a r ds(on) v gs = 10 v, i d = 1.5 a 0.199 0.195 : v gs = 6 v, i d = 1 a 0.222 0.222 forward transconductance a g fs v ds = 20 v, i d = 4.6 a 3 2 s body diode voltage v sd i s = 1.3 a 0.79 0.80 v dynamic b input capacitance c iss v ds = 20 v, v gs = 0 v, f = 1 mhz 190 190 pf output capacitance c oss 22 22 reverse transfer capacitance c rss 15 13 total gate charge q g v ds = 50 v, v gs = 10 v, i d = 1.6 a 4.1 5.2 nc v ds = 50 v, v gs = 4.5 v, i d = 1.6 a 2.5 2.9 gate-source charge q gs 0.75 0.75 gate-drain charge q gd 1.4 1.4
|
